1. Field of the Invention
The present invention generally relates to general purpose digital data processing systems and more particularly relates to such systems which execute multiple programs.
2. Description of the Prior Art
It is now common in large scale data processing systems to permit software developers to treat real storage as virtual memory. This is a technique wherein all memory accesses by a specific user program are relative in nature. The major advantage of this approach is that memory management can be efficiently performed by the system at the time of program execution depending upon resource availability and requests from other users. The memory management process appears transparent to the user. The 2200/600 system available from the assignee of the present invention, and incorporated herein by reference, is such a system employing virtual addressing.
U.S. Pat. No. 4,827,406 issued to Bischoff et al, shows one method of handling virtual addressing. It is currently most desirable to structure an architecture in which the software makes address references relative to an addressing environment which can be readily loaded along with the program and can be modified during program operation as necessary. The actual physical memory space must be addressed, of course, using an absolute rather than a relative address. To accomplish this, the virtual (or relative) address is converted to an absolute address using a translation table. A typical translation scheme is shown in U.S. Pat. No. 4,827,400 issued to Dunwell et al.
Further convenience and performance enhancements occur by dividing the virtual address space into fixed length pages and by dividing the real address space into blocks. The system is thus enhanced by providing logical divisions for programming purposes while accessing main memory by a hardware efficient block size. The conversion hardware efficiently performs the required translations without subjecting the user to the resulting bookkeeping. As a result, the storage resources of the system are efficiently managed in real time without unnecessary concern by the users.
The registers which store the data permitting conversion from the virtual address of a software program to the real address used by the physical storage system are assumed to be unique to that software program. The virtual address for a program or operand segment is loaded into the active base table. The corresponding absolute address of the segment is computed and placed into a base register. As different programs are loaded and run, the contents of these registers must be modified. Similarly, the contents of one or more of the registers may need to be modified during the operation of a given program to permit access to different segments of data located at different virtual addresses. U.S. Pat. No. 4,862,349 issued to Foreman et al, shows a technique for user modification of control block data. However, care must be exercised to prevent one program from inadvertently impacting another, unrelated program. U.S. Pat. No. 4,835,677 issued to Sato et al, shows a typical hardware protection approach. Notification to multiple users of a General Purpose Register set is provided by the technique of U.S. Pat. No. 4,903,194 issued to Pomerene et al.
User modification of address translation tables must be accompanied by modification of addressing limits to maintain data security. Furthermore, it is desirable that the user program be permitted to change the conversion tables using virtual addressing. Unfortunately, complete modification of all of these quantities consumes a substantial amount of processor capacity. Studies have shown that as many as 85% of the base register modification operations during the execution of a particular user program change only the offset within a bank. Yet prior art systems continue to modify all of the conversion variables.
A common opportunity for changing the data registers which translate virtual to absolute addresses is during interrupts which transition the processor from one state to another, and at the initiation of an application program after the partial or complete run of a different and unrelated application program. The assignee of the present invention has for some time provided systems wherein the executive and user states have dedicated registers to mitigate a portion of this problem. A less efficient approach may be found in U.S. Pat. No. 4,825,358 issued to Letwin. U.S. Pat. No. 4,853,849 issued to Bain, Jr. et al, shows an alternative technique for input/output transfers.
Most modern large scale data processing systems also employ some form of microprocessing and pipelining. U.S. Pat. No. 4,825,363 issued to Baumann et al, and U.S. Pat. No. 4,841,436 issued to Asano et al, show microprocessor based architectures. U.S. Pat. No. 4,890,221 issued to Gage and U.S. Pat. No. 4,939,640 issued to Bachman et al, show architectures wherein the environment is saved by storing all of the variables.